Exposed Pads: A Brief Introduc
abstract: many of maxim's recent ics have exposed pad packages. as there have been many questions from our customers on dealing with the exposed pad, this note attempts to provide some general advice.
an exposed pad is an exposed metal plate on an ic package. this application note focuses on pads that are located on the bottom of the package. exposed pads on the top of the package are less common and their data sheets provide the information the designer needs. for the sake of this application note, consider all pads to be on the bottom, or pcb side of the ic package. the exposed pad is plated with the same metal or metal alloy as the leads of the ic, usually tin. exposed pads are found on many types of packages. mature package types with gull wing leads, such as tssop, offer exposed pads as an optional configuration. on datasheets with tssop packages and exposed pads, we are careful to note there is an exposed pad, and the pcb designer must make provisions for its use. the exposed pad is a standard part of tdfn and qfn packages. they always have exposed pads. exposed pads increase the maximum power dissipation of packages. when an exposed pad is offered as an option, it is specifically to increase the power dissipation capabilities of the ic package. (for packages which always have the pad, the pad may or may not be needed for power dissipation. for example, a low-power op amp may see a worst-case power dissipation under 50mw, but be housed in a package capable of safely dissipating over a watt.) the datasheet for a device with an exposed pad will provide instruction as to the voltage to which the exposed pad should be connected. in most applications, the exposed pad is connected to ground, but be careful to verify this on every device! a blind assumption here can provide a low-impedance short which can take many hours to analyze and a pcb revision to correct. the pad's dimensions come from the package drawing. some of maxim's exposed pad packages have variants with different-sized exposed pads. if the datasheet is not explicit as to which variant is used, contact maxim/dallas applications tech support to obtain further information. create the pcb footprint with information from ipc to ensure proper allowances for both ic package tolerance and process variance. in addition to the ipc information, here are some general guidelines for creating the exposed pad's land pattern: the pad should be large enough to accommodate the entire exposed pad. this provides a uniform mounting surface as well as a functional keepout area of traces underneath an exposed pad package. on ics which don't need the additional power dissipation of the exposed pad the pad should still be created and connected to the required potential. this eliminates the chance of inadvertently shorting the exposed pad to traces which are routed underneath it. on ics where the exposed pad is intended to provide significant power dissipation, the pcb designer should add vias from the exposed pad's land area to a copper polygon on the other side of the pcb. this provides lower thermal impedance from the ic to the ambient air. when creating the solder paste screen, an opening should be created for the exposed pad. this way the exposed pad will be electrically and thermally connected to the pcb. if the board must be hand assembled, a small amount of electrically conductive adhesive can be used, but this makes rework of the pcb virtually impossible. another alternative to facilitate hand assembly is to include a single large via in the center of the land to allow the application of a soldering iron to the bottom of the ic through this hole. this is a compromise, and should only be used when necessary. the best approach is to use a standard smt assembly process with carefully controlled parameters to ensure reliable and repeatable results.
三星电子希望超越台积电的计划距离越来越遥远
流量计的动态原理图以及产品特点
NFV和云环境之间有着怎样的差异
电流互感器二次开路的原因和解决办法
基于复杂可编程逻辑器件的VME总线接口逻辑系统的设计
Exposed Pads: A Brief Introduc
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由MCU控制的TOPSwitch?FZ单片开关电源电路图
固态氧化物燃料电池和CIGS太阳能电池薄膜材料简介
一文详解精密整流电路
an exposed pad is an exposed metal plate on an ic package. this application note focuses on pads that are located on the bottom of the package. exposed pads on the top of the package are less common and their data sheets provide the information the designer needs. for the sake of this application note, consider all pads to be on the bottom, or pcb side of the ic package. the exposed pad is plated with the same metal or metal alloy as the leads of the ic, usually tin. exposed pads are found on many types of packages. mature package types with gull wing leads, such as tssop, offer exposed pads as an optional configuration. on datasheets with tssop packages and exposed pads, we are careful to note there is an exposed pad, and the pcb designer must make provisions for its use. the exposed pad is a standard part of tdfn and qfn packages. they always have exposed pads. exposed pads increase the maximum power dissipation of packages. when an exposed pad is offered as an option, it is specifically to increase the power dissipation capabilities of the ic package. (for packages which always have the pad, the pad may or may not be needed for power dissipation. for example, a low-power op amp may see a worst-case power dissipation under 50mw, but be housed in a package capable of safely dissipating over a watt.) the datasheet for a device with an exposed pad will provide instruction as to the voltage to which the exposed pad should be connected. in most applications, the exposed pad is connected to ground, but be careful to verify this on every device! a blind assumption here can provide a low-impedance short which can take many hours to analyze and a pcb revision to correct. the pad's dimensions come from the package drawing. some of maxim's exposed pad packages have variants with different-sized exposed pads. if the datasheet is not explicit as to which variant is used, contact maxim/dallas applications tech support to obtain further information. create the pcb footprint with information from ipc to ensure proper allowances for both ic package tolerance and process variance. in addition to the ipc information, here are some general guidelines for creating the exposed pad's land pattern: the pad should be large enough to accommodate the entire exposed pad. this provides a uniform mounting surface as well as a functional keepout area of traces underneath an exposed pad package. on ics which don't need the additional power dissipation of the exposed pad the pad should still be created and connected to the required potential. this eliminates the chance of inadvertently shorting the exposed pad to traces which are routed underneath it. on ics where the exposed pad is intended to provide significant power dissipation, the pcb designer should add vias from the exposed pad's land area to a copper polygon on the other side of the pcb. this provides lower thermal impedance from the ic to the ambient air. when creating the solder paste screen, an opening should be created for the exposed pad. this way the exposed pad will be electrically and thermally connected to the pcb. if the board must be hand assembled, a small amount of electrically conductive adhesive can be used, but this makes rework of the pcb virtually impossible. another alternative to facilitate hand assembly is to include a single large via in the center of the land to allow the application of a soldering iron to the bottom of the ic through this hole. this is a compromise, and should only be used when necessary. the best approach is to use a standard smt assembly process with carefully controlled parameters to ensure reliable and repeatable results.
三星电子希望超越台积电的计划距离越来越遥远
流量计的动态原理图以及产品特点
NFV和云环境之间有着怎样的差异
电流互感器二次开路的原因和解决办法
基于复杂可编程逻辑器件的VME总线接口逻辑系统的设计
Exposed Pads: A Brief Introduc
光耦在电路中起到什么作用？
多功能一体机的复印分辨率
石油专题——石油测井高温线性电源工艺及特色
把芯片当成乐高？英特尔新思维背后的技术进步
新唐科技NUC442KI8AE控制器简介
苹果Pro Display XDR显示器4999美元起
向“别人家的XX”说不 智能家居我做主
长光辰芯推出小面阵全局快门CMOS图像传感器
51单片机的最小系统应用说明
中国制造如何？德媒一文介绍中国制造的实力
RA MCU CANFD的应用实例（上）
由MCU控制的TOPSwitch?FZ单片开关电源电路图
固态氧化物燃料电池和CIGS太阳能电池薄膜材料简介
一文详解精密整流电路