ADI AD9547网络时钟发生与同步方案
adi 公司的ad9547是双路/四路输入网络时钟发生器/同步器,能为许多系统包括同步光网络(sonet/sdh)提供同步.输入基准频率从1 khz 到750 mhz,频率监视1ppm,输出频率高达450mhz,主要应用在网络同步,oc-192的sonet/sdh时钟,无线基站,控制器,有线基础设备和数据通信. 本文介绍了ad9547主要特性, 功能方框图,详细方框图, 输出同步方框图和评估板电路图以及评估板材料清单.
ad9547: dual/quad input network clock generator/synchronizer
the ad9547 provides synchronization for many systems, including synchronous optical networks (sonet/sdh). the ad9547 generates an output clock that is synchronized to one of two differential or four single-ended external input references. the digital pll allows for reduction of input time jitter or phase noise associated with the external references. the ad9547 continuously generates a clean (low jitter), valid output clock, even when all references fail, by means of digitally controlled loop and holdover circuitry. the ad9547 operates over an industrial temperature range of −40℃ to +85℃.
ad9547主要特性:
supports stratum 2 stability in holdover mode
supports reference switchover with phase build-out
supports hitless reference switchover
automatic/manual holdover and reference switchover
2 pairs of reference input pins, with each pair configurable as a single differential input or as 2 independent single-ended inputs
input reference frequencies from 1 khz to 750 mhz
reference validation and frequency monitoring (1 ppm)
programmable input reference switchover priority
30-bit programmable input reference divider
2 pairs of clock output pins, with each pair configurable as a single differential lvds/lvpecl output or as 2 single-ended cmos outputs
output frequencies up to 450 mhz
20-bit integer and 10-bit fractional programmable feedback divider
programmable digital loop filter covering loop bandwidths from 0.001 hz to 100 khz
optional low noise lc-vco system clock multiplier
optional crystal resonator for system clock input
on-chip eeprom to store multiple power-up profiles
software controlled power-down
64-lead lfcsp package
ad9547应用:
network synchronization
cleanup of reference clock jitter
sonet/sdh clocks up to oc-192, including fec
stratum 2 holdover, jitter cleanup, and phase transient control
stratum 3e and stratum 3 reference clocks
wireless base stations, controllers
cable infrastructure
data communications
图1.ad9547功能方框图
图2.ad9547详细方框图
图3.ad9547输出同步方框图
图4.ad9547评估板电路图(1)
图5.ad9547评估板电路图(2)
图6.ad9547评估板电路图(3)
ad9547评估板材料清单(bom)见:
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ad9547: dual/quad input network clock generator/synchronizer
the ad9547 provides synchronization for many systems, including synchronous optical networks (sonet/sdh). the ad9547 generates an output clock that is synchronized to one of two differential or four single-ended external input references. the digital pll allows for reduction of input time jitter or phase noise associated with the external references. the ad9547 continuously generates a clean (low jitter), valid output clock, even when all references fail, by means of digitally controlled loop and holdover circuitry. the ad9547 operates over an industrial temperature range of −40℃ to +85℃.
ad9547主要特性:
supports stratum 2 stability in holdover mode
supports reference switchover with phase build-out
supports hitless reference switchover
automatic/manual holdover and reference switchover
2 pairs of reference input pins, with each pair configurable as a single differential input or as 2 independent single-ended inputs
input reference frequencies from 1 khz to 750 mhz
reference validation and frequency monitoring (1 ppm)
programmable input reference switchover priority
30-bit programmable input reference divider
2 pairs of clock output pins, with each pair configurable as a single differential lvds/lvpecl output or as 2 single-ended cmos outputs
output frequencies up to 450 mhz
20-bit integer and 10-bit fractional programmable feedback divider
programmable digital loop filter covering loop bandwidths from 0.001 hz to 100 khz
optional low noise lc-vco system clock multiplier
optional crystal resonator for system clock input
on-chip eeprom to store multiple power-up profiles
software controlled power-down
64-lead lfcsp package
ad9547应用:
network synchronization
cleanup of reference clock jitter
sonet/sdh clocks up to oc-192, including fec
stratum 2 holdover, jitter cleanup, and phase transient control
stratum 3e and stratum 3 reference clocks
wireless base stations, controllers
cable infrastructure
data communications
图1.ad9547功能方框图
图2.ad9547详细方框图
图3.ad9547输出同步方框图
图4.ad9547评估板电路图(1)
图5.ad9547评估板电路图(2)
图6.ad9547评估板电路图(3)
ad9547评估板材料清单(bom)见:
荣耀8青春版评测：千元神机荣耀8青春版和小米中的红米Note 4x谁强谁弱？
贸联潜力转接产品与精品级家电用连接器 有助迎接未来物联网商机
智慧养殖环境监测系统
EVCVTS B110北斗三代手持机的参数配置
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差分隐私和现有的隐私保护方法相结合：从用户群体中学习的系统架构详解
高效框架互操作性第2部分：数据加载传输瓶颈和RDMA解决方案
立体声信号相位差电平差测试仪设计方案
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中国联通发布了2018-2020年通信云新建工程硬件采购项目
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LDO如何实现输出过载保护？
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