Parallel-Port Interface Powers
abstract: a sot step-down dc-dc converter efficiently steals power from a parallel port while a sim/smart card level shift integrated circuit (ic) completes the interface. this allows the parallel port to power, and communicate with, low voltage logic. the same techniques can also be applied to usb designs.
for portable-sensing and data-acquisition applications, a laptop computer and its parallel port (lpt) make good bedfellows. yet in the effort to extend battery life, many microprocessors and entire systems operate with logic levels down to 1.8v. the lpt port's 5v output signals don't easily support the low-voltage logic required to increase battery life and achieve longer data-acquisition times.
because dynamic power consumption for a microprocessor or clocked circuit is predominately a function of voltage (p = cv²f), logic systems that operate off the parallel port at below 5v can substantially conserve power. the circuit shown in the figure accepts data from the lpt port and delivers up to 100ma at 2v. efficiency is as high as 94%. translating 5v logic levels at the lpt-port data pins down to 2v, the circuit also offers esd protection.
the low-voltage surface-mount ic labeled u1—a step-down dc-dc converter with built-in mosfets and a synchronous rectifier—forms a simple and highly efficient 2v source. feedback resistors r1 and r2 set the output voltage as low as 1.25 v. (voltage is set at 2v in the example circuit.) u1's shutdown pin connects directly to bit d1 of the 5v lpt control port (pin 14), letting the device be enabled and disabled with software.
when enabled, u1's soft-start capability limits the inrush current. schottky diodes d1 through d3 act in conjunction with pins 5 through 9 of the 5v lpt data port to provide power for the converter. software also easily enables and disables the data-port pins.
as a low-voltage sim/smart-card level translator, u2 translates the logic levels from 5 to 2v. u2 also provides esd protection to the inputs. the input side of the low-voltage translator operates at 5v logic levels and is powered by input capacitor c1 at approximately 5v. u2's output side is powered by the 2v supply. data is read into the lpt status port (pin 12) serially; clock (clk) and chip-select (active-low cs) signals are derived from the lpt data port and software.
the example data interface consists of an 8-bit parallel-load shift register (u3) and an open-drain logic gate (u4). it reads u2's i/o pin and supplies parallel data. software in the pc toggles the clk and active-low cs lines to load and shift this parallel data into the program. the c++ software and text is configured to convert parallel data from the shift register to a serial format. after minor modifications, however, it can be configured to support a microcontroller interface or a serial spi, i²c, or smbus interface.
therefore, this circuit can send data to an spi, i²c, or smbus serial interface, or to an 8-bit parallel-out serial shift register such as the sn74hc164, which can operate at 2v. many devices available today take advantage of these power savings by operating down to 1.5v.
figure 1. to save power, this circuit converts the 5v lpt parallel interface of a laptop computer to a parallel interface operating at a lower voltage.
a similar version of this article appeared in the june 24, 2002 issue of electronic design magazine.
俄罗斯无人机送快递测试撞墙
国内大功率晶闸管什么品牌比较好
灵云全智能能力平台之语音识别（ASR）能力服务
抢占手机新风口华为“押宝”5G可折叠手机
电子芯闻早报：够执着，紫光仍在努力收购美光
Parallel-Port Interface Powers
百度AI芯片业务的最新进展
如何通过燃料电池堆栈将氢能转换成电能
计算机软件研发与系统集成企业博通股份发布2022第一季度报告
国能惠选上市，引领新能源领域的投资风向标
粮食重金属测定仪的产品特点是什么
万达宣布彻底告别房地产，发展轻资产，马云涉及房屋租赁，只想问房价是涨是跌？
宝马凭借SABIC的轻质材料，获得内饰类别大奖
2023年1月国内动力电池装机量分析
联芯科技双核A9智能终端芯片通过中移动芯片LC1810
部分台厂淡出 预估第二季大尺寸面板出货量再减
如何为车辆ADAS设计更好的高电流开关电源
新迪数字使命在肩，如何用硬核实力提供“软”支持
什么是光伏配电箱 如何检测家用配电箱跳闸问题
大众神车也加长？大众途观L试驾
for portable-sensing and data-acquisition applications, a laptop computer and its parallel port (lpt) make good bedfellows. yet in the effort to extend battery life, many microprocessors and entire systems operate with logic levels down to 1.8v. the lpt port's 5v output signals don't easily support the low-voltage logic required to increase battery life and achieve longer data-acquisition times.
because dynamic power consumption for a microprocessor or clocked circuit is predominately a function of voltage (p = cv²f), logic systems that operate off the parallel port at below 5v can substantially conserve power. the circuit shown in the figure accepts data from the lpt port and delivers up to 100ma at 2v. efficiency is as high as 94%. translating 5v logic levels at the lpt-port data pins down to 2v, the circuit also offers esd protection.
the low-voltage surface-mount ic labeled u1—a step-down dc-dc converter with built-in mosfets and a synchronous rectifier—forms a simple and highly efficient 2v source. feedback resistors r1 and r2 set the output voltage as low as 1.25 v. (voltage is set at 2v in the example circuit.) u1's shutdown pin connects directly to bit d1 of the 5v lpt control port (pin 14), letting the device be enabled and disabled with software.
when enabled, u1's soft-start capability limits the inrush current. schottky diodes d1 through d3 act in conjunction with pins 5 through 9 of the 5v lpt data port to provide power for the converter. software also easily enables and disables the data-port pins.
as a low-voltage sim/smart-card level translator, u2 translates the logic levels from 5 to 2v. u2 also provides esd protection to the inputs. the input side of the low-voltage translator operates at 5v logic levels and is powered by input capacitor c1 at approximately 5v. u2's output side is powered by the 2v supply. data is read into the lpt status port (pin 12) serially; clock (clk) and chip-select (active-low cs) signals are derived from the lpt data port and software.
the example data interface consists of an 8-bit parallel-load shift register (u3) and an open-drain logic gate (u4). it reads u2's i/o pin and supplies parallel data. software in the pc toggles the clk and active-low cs lines to load and shift this parallel data into the program. the c++ software and text is configured to convert parallel data from the shift register to a serial format. after minor modifications, however, it can be configured to support a microcontroller interface or a serial spi, i²c, or smbus interface.
therefore, this circuit can send data to an spi, i²c, or smbus serial interface, or to an 8-bit parallel-out serial shift register such as the sn74hc164, which can operate at 2v. many devices available today take advantage of these power savings by operating down to 1.5v.
figure 1. to save power, this circuit converts the 5v lpt parallel interface of a laptop computer to a parallel interface operating at a lower voltage.
a similar version of this article appeared in the june 24, 2002 issue of electronic design magazine.
俄罗斯无人机送快递测试撞墙
国内大功率晶闸管什么品牌比较好
灵云全智能能力平台之语音识别（ASR）能力服务
抢占手机新风口华为“押宝”5G可折叠手机
电子芯闻早报：够执着，紫光仍在努力收购美光
Parallel-Port Interface Powers
百度AI芯片业务的最新进展
如何通过燃料电池堆栈将氢能转换成电能
计算机软件研发与系统集成企业博通股份发布2022第一季度报告
国能惠选上市，引领新能源领域的投资风向标
粮食重金属测定仪的产品特点是什么
万达宣布彻底告别房地产，发展轻资产，马云涉及房屋租赁，只想问房价是涨是跌？
宝马凭借SABIC的轻质材料，获得内饰类别大奖
2023年1月国内动力电池装机量分析
联芯科技双核A9智能终端芯片通过中移动芯片LC1810
部分台厂淡出 预估第二季大尺寸面板出货量再减
如何为车辆ADAS设计更好的高电流开关电源
新迪数字使命在肩，如何用硬核实力提供“软”支持
什么是光伏配电箱 如何检测家用配电箱跳闸问题
大众神车也加长？大众途观L试驾