FPGA专家教您如何在FPGA设计中使用HLS
luke miller并非一开始就是hls（高层次综合）的倡导者。在使用早期的工具版本的时候，他似乎有过一些糟糕的经历。他写道： “……我的心筑起心墙，我需要帮助。”幸运的是，现在的他似乎已经通过了一个12步hls培训活动， 现在可以利用xilinx vivado hls有效地开展工作了。
semiwiki 有了一位新的博主，被称为“the fpga expert（fpga专家）”。通过linkedin简单搜索，我得知这位fpga专家是luke miller，他最近发表了一篇博文，介绍如何使用高层次综合（hls）开发从c到其他hll版本的各种加速硬件。 虽然不像“手把手的菜谱”那样具体详尽，但依然非常有趣。
miller曾经在ibm公司担任过asic设计师，在lockheed担任过硬件师（工程师/架构师），目前是一位拥有军事和航空设计经验的pe。miller的网站名为fpga expert，上面有一段特别的讲述其个人经历的视频，其中描述了多项军事、航空和医疗项目（飞机、雷达和医疗成像），所以，我猜他应该拥有非常丰富的fpga设计经验。他的网站证实了这个猜想。 miller似乎也非常了解hls。他写道：
“设计时间的加速并非从c到vhdl的转换， 真正起到关键因素的是仿真域 —您再也无需通过rtl逐件验证每项设计。”
luke miller并非一直都是hls（高层次综合）的倡导者。在使用早期的工具版本的时候，他似乎有些糟糕的经历。。他写道：“……我的心筑起心墙，我需要帮助。”幸运的是，他似乎已经通过了一个12步hls培训活动， 现在可以通过xilinx vivado hls有效地开展工作了。
点击此处，阅读miller有关hls的建议：“高层次综合 —它真的行！ （ high level synthesis – it’s for real） ”%96-%92s-real.html
下面是miller的全文供参考：
======================================================================================
high level synthesis – it’s for real
by
thefpgaexpert
published on 04-11-2013 06:30 pm
it was spring 2010 and i was asked to attend an hls (high level synthesis) meeting. to be honest i cringed, after my bad relationship with accel dsp and broken promises my heart was all walled up and needed counseling. but my management had a way of making me an offer i could not refuse, like keeping my job. so reluctantly i went. does your employer do lunch and learns instead of real training? you know what that equals right? a 1/8 pay cut, but let’s play nice.
anyways after the usual introductions at the meeting they began to get into the meat of the tool. i quickly diverted and asked if we could see the tool in action and move away from the power point and boy did they. first up was a cookie cutter fir filter but it worked, really! then they moved into floating point designs etc. this hls was the greatest thing since sliced bread. i saw its potential and i needed to try it. we all agreed on an evaluation period. now i am by no means the best coder in the world, but even the best would have a hard time beating the hls tool with respect to design time, area and latency.
what hls is not: it is not a coder in a box, thus sit down the software guy and have him designing fpgas. you need to understand the fpga, no exceptions or you will have a fat, slow design. the c or its variant will need to be restructured, smartly, thus helping the tool out so it can perform better. it is not a button you press and you have a bit image. i know how program managers think.
i leverage hls tools in this fashion. i view it as xilinx corgen on steroids which are driven by a c file. the speed up in design time is not in the translation from c to vhdl but really is in the simulation domain. you are no longer verifying designs piece by piece using rtl. for example, i design a beamfomer in c. i compile it and then run ‘a.exe’ and verify that the answer matches the expects. that took about a second. for many pris of data that could of taken hours in modelsim. catching on? i then bring up the hls tool and pull in the c file and the tool reports the latency, area, clock frequency etc. from that information i can determine which fpga to use. i then start using directives to optimize the area / latency by using unrolls and pipeline directives. about an hour later my beamformer is done. i then simulate the rtl at my top level but i already know the math works and the tool took care of the boundary conditions. the goal of this article is by no means a recipe on hls usage but hopefully entices you to check it out, you won’t be sorry.
钠离子电池优点及发展现状
物联网怎样来守护桥梁安全
多种栅极驱动供电选项和基本驱动要求
缺货潮后，芯片买家旧习难改
TDA2030A功放板原理图
FPGA专家教您如何在FPGA设计中使用HLS
全球供应链透明化的技术关键及应用实现
使用Cache的必要性与可行性
碳化硅SiC的高温氧化研究
韩媒担忧华为降低三星依赖，更多采购本土厂商元器件
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万用表的使用方法以及注意事项
多功能食品安全检测仪的特点
大疆又搞机，这款无人机体积小但活超好
SharePointOnline到SharePointOnline的迁移过程
基于CXL的直接访问高性能内存分解框架
FPGA在汽车核心电子系统中的机遇
紫外线传感器在紫外辐射照度计中的应用分析
你知道R型干式变压器的分类有哪些吗？
ASML供应商Prodrive发生火灾 供货日期被推迟
semiwiki 有了一位新的博主，被称为“the fpga expert（fpga专家）”。通过linkedin简单搜索，我得知这位fpga专家是luke miller，他最近发表了一篇博文，介绍如何使用高层次综合（hls）开发从c到其他hll版本的各种加速硬件。 虽然不像“手把手的菜谱”那样具体详尽，但依然非常有趣。
miller曾经在ibm公司担任过asic设计师，在lockheed担任过硬件师（工程师/架构师），目前是一位拥有军事和航空设计经验的pe。miller的网站名为fpga expert，上面有一段特别的讲述其个人经历的视频，其中描述了多项军事、航空和医疗项目（飞机、雷达和医疗成像），所以，我猜他应该拥有非常丰富的fpga设计经验。他的网站证实了这个猜想。 miller似乎也非常了解hls。他写道：
“设计时间的加速并非从c到vhdl的转换， 真正起到关键因素的是仿真域 —您再也无需通过rtl逐件验证每项设计。”
luke miller并非一直都是hls（高层次综合）的倡导者。在使用早期的工具版本的时候，他似乎有些糟糕的经历。。他写道：“……我的心筑起心墙，我需要帮助。”幸运的是，他似乎已经通过了一个12步hls培训活动， 现在可以通过xilinx vivado hls有效地开展工作了。
点击此处，阅读miller有关hls的建议：“高层次综合 —它真的行！ （ high level synthesis – it’s for real） ”%96-%92s-real.html
下面是miller的全文供参考：
======================================================================================
high level synthesis – it’s for real
by
thefpgaexpert
published on 04-11-2013 06:30 pm
it was spring 2010 and i was asked to attend an hls (high level synthesis) meeting. to be honest i cringed, after my bad relationship with accel dsp and broken promises my heart was all walled up and needed counseling. but my management had a way of making me an offer i could not refuse, like keeping my job. so reluctantly i went. does your employer do lunch and learns instead of real training? you know what that equals right? a 1/8 pay cut, but let’s play nice.
anyways after the usual introductions at the meeting they began to get into the meat of the tool. i quickly diverted and asked if we could see the tool in action and move away from the power point and boy did they. first up was a cookie cutter fir filter but it worked, really! then they moved into floating point designs etc. this hls was the greatest thing since sliced bread. i saw its potential and i needed to try it. we all agreed on an evaluation period. now i am by no means the best coder in the world, but even the best would have a hard time beating the hls tool with respect to design time, area and latency.
what hls is not: it is not a coder in a box, thus sit down the software guy and have him designing fpgas. you need to understand the fpga, no exceptions or you will have a fat, slow design. the c or its variant will need to be restructured, smartly, thus helping the tool out so it can perform better. it is not a button you press and you have a bit image. i know how program managers think.
i leverage hls tools in this fashion. i view it as xilinx corgen on steroids which are driven by a c file. the speed up in design time is not in the translation from c to vhdl but really is in the simulation domain. you are no longer verifying designs piece by piece using rtl. for example, i design a beamfomer in c. i compile it and then run ‘a.exe’ and verify that the answer matches the expects. that took about a second. for many pris of data that could of taken hours in modelsim. catching on? i then bring up the hls tool and pull in the c file and the tool reports the latency, area, clock frequency etc. from that information i can determine which fpga to use. i then start using directives to optimize the area / latency by using unrolls and pipeline directives. about an hour later my beamformer is done. i then simulate the rtl at my top level but i already know the math works and the tool took care of the boundary conditions. the goal of this article is by no means a recipe on hls usage but hopefully entices you to check it out, you won’t be sorry.
钠离子电池优点及发展现状
物联网怎样来守护桥梁安全
多种栅极驱动供电选项和基本驱动要求
缺货潮后，芯片买家旧习难改
TDA2030A功放板原理图
FPGA专家教您如何在FPGA设计中使用HLS
全球供应链透明化的技术关键及应用实现
使用Cache的必要性与可行性
碳化硅SiC的高温氧化研究
韩媒担忧华为降低三星依赖，更多采购本土厂商元器件
上位机什么意思 上位机功能介绍
万用表的使用方法以及注意事项
多功能食品安全检测仪的特点
大疆又搞机，这款无人机体积小但活超好
SharePointOnline到SharePointOnline的迁移过程
基于CXL的直接访问高性能内存分解框架
FPGA在汽车核心电子系统中的机遇
紫外线传感器在紫外辐射照度计中的应用分析
你知道R型干式变压器的分类有哪些吗？
ASML供应商Prodrive发生火灾 供货日期被推迟